#ifndef __S5PV210_REG_CLK_H__
#define __S5PV210_REG_CLK_H__

#define S5PV210_CLK_BASE	(0xe0100000)

#define CLK_APLL_LOCK		(0x0000)
#define CLK_MPLL_LOCK		(0x0008)
#define CLK_EPLL_LOCK		(0x0010)
#define CLK_VPLL_LOCK		(0x0020)
#define CLK_APLL_CON0		(0x0100)
#define CLK_APLL_CON1		(0x0104)
#define CLK_MPLL_CON		(0x0108)
#define CLK_EPLL_CON0		(0x0110)
#define CLK_EPLL_CON1		(0x0114)
#define CLK_VPLL_CON		(0x0120)
#define CLK_SRC0			(0x0200)
#define CLK_SRC1			(0x0204)
#define CLK_SRC2			(0x0208)
#define CLK_SRC3			(0x020C)
#define CLK_SRC4			(0x0210)
#define CLK_SRC5			(0x0214)
#define CLK_SRC6			(0x0218)
#define CLK_SRC_MASK0		(0x0280)
#define CLK_SRC_MASK1		(0x0284)
#define CLK_DIV0			(0x0300)
#define CLK_DIV1			(0x0304)
#define CLK_DIV2			(0x0308)
#define CLK_DIV3			(0x030C)
#define CLK_DIV4			(0x0310)
#define CLK_DIV5			(0x0314)
#define CLK_DIV6			(0x0318)
#define CLK_DIV7			(0x031C)
#define CLK_GATE_IP0		(0x0460)
#define CLK_GATE_IP1		(0x0464)
#define CLK_GATE_IP2		(0x0468)
#define CLK_GATE_IP3		(0x046C)
#define CLK_GATE_IP4		(0x0470)
#define CLK_GATE_BLOCK		(0x0480)
#define CLK_GATE_IP5		(0x0484)
#define CLK_OUT				(0x0500)
#define CLK_STAT0			(0x1000)
#define CLK_STAT1			(0x1004)
#define CLK_MUX_STAT0		(0x1100)
#define CLK_MUX_STAT1		(0x1104)

#endif /* __S5PV210_REG_CLK_H__ */
